1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same.
2. Description of the Prior Art
In recent years, the development of semiconductor devices in which numerous elements are integrated at a high density on a semiconductor chip has been actively under way. For the memory cell of the dynamic random access memory (DRAM), there have been proposed various structures suitable for miniaturization of the device.
Presently, the preferred memory cell from the standpoint of minimum area is the one transistor and one capacitor cell. In such a memory cell, signal charge is stored in the storage node of the capacitor (storage capacitor) connected to the transistor (switching transistor).
The storage node of the memory cell is required to have a surface area larger than a prescribed value. Therefore, further progress in the miniaturization of the memory cell makes it imperative for a storage node having a relatively large surface area to be formed within a small, restricted region on a semiconductor substrate.
The stacked memory cell in which the storage node is formed above a silicon substrate is suitable for higher integration of memory cells and has the advantage of being less likely to cause soft errors. Furthermore, the stacked memory cell has an advantage compared to the trench type memory cell having a trench capacitor in that the former is relatively easy to fabricate and suitable for mass production.
For the stacked memory cells, there has been proposed, for example, a memory cell having a fin structure (T, Ema et. al., "3-DIMENSIONAL SPARKED CAPACITOR CELL FOR 16M AND 64M DRAMS", IEEE International Electron Device Meeting Technical Digest, p.592-595, December 1988). The memory cell has a structure in which the surface area of the storage node is larger than the area on the substrate occupied by the memory cell.
Referring to FIGS. 5A to 5E, we will now describe a prior art semiconductor device having the above-mentioned fin structure. FIG. 5A shows in cross section a fragmentary portion of a p-type substrate 1 on which a switching transistor 50 is formed. The switching transistor 50 is an n-type MOSFET having n-type impurity diffusion layers 4 and a word line 3 that also serves as the gate electrode of the switching transistor 50. The switching transistor 50 is electrically isolated from other switching transistors (not shown) by an isolation oxide 2 formed on the p-type substrate 1.
An insulating layer 5-A is deposited by a CVD technique on isolation oxide 2 in such a manner as to cover the switching transistor 50, after which an Si.sub.3 N.sub.4 film 5-B, a first silicon oxide film 6-A, a first silicon film 7-A, and a second silicon oxide film 6-B are deposited in this order on top of the Si.sub.3 N.sub.4 film 5-B starting from the side of the P-type substrate 1.
A contact window 8 is formed in the multilayer structure comprising the above-mentioned films, as shown in FIG. 5B. Thereafter, a second silicon film 7-B is deposited on top of the second silicon oxide film 6-B in such a manner as to contact the n-type impurity diffusion layer 4 of the switching transistor 50 through the contact window 8, as shown in FIG. 5C.
Next, after patterning the second silicon film 7-B by an anisotropic etching technique with a resist mask 9, the second silicon oxide film 6-B is etched away. Also, after patterning the first silicon film 7-A, the first silicon oxide film 6-A is etched away (FIG. 5D), thus forming a storage node 10 having a fin structure. Then, a dielectric film 11 and a cell plate 12 are formed in this order on top of the storage node 10, to form a storage capacitor as shown in FIG. 5E. After the storage capacitor is formed, a bit line 13 is formed to interconnect the switching transistor 50 to the periphery circuit (not shown).
The storage node 10 of the prior art semiconductor memory device has sharp edges in cross section perpendicular to the top surface of the p-type substrate 1, as shown in FIG. 6A. Each of the sharp edges is constituted by two faces of many faces of the storage node 10. One of the two faces is formed by isotropic etching and is substantially perpendicular to the top surface of the p-type substrate 1, and the other is substantially parallel to the top surface of the p-type substrate 1.
Due to the existence of the sharp edges of the storage node 10, electric field concentrations occur in the vicinity of the shape edges. The electric field concentrations cause the dielectric film 11 to break down at a low voltage applied between the storage node 10 and the cell plate 12. Especially, when the dielectric film 11 is an oxide film which is formed by oxidizing the surface of the storage node 10 in an oxidizing ambient with a temperature of about 850.degree. C. or more, the edges become sharper due to a hone effect which occurs during oxidizing the shape edges. This hone effect is referred to in detail in Extended Abstracts of the 16th (1984) International Conference on Solid State Devices and Materials, Kobe, 1984, pp.475-478.
FIG. 6B schematically shows the electric field concentration in the vicinity of a sharp edge of the storage node 10. The degree of the electric concentration, i.e., the ratio of a peak value of an electric field strength (E.sub.EDGE) in the vicinity of the edge to an electric field strength (E.sub.FLAT) in a flat region of the storage node 10, is dependent upon the angle (.theta.) of the edge. The relationship between the ratio (E.sub.EDGE /E.sub.FLAT) and the angle (.theta.) of the edge is shown in FIG. 7. This relationship was obtained by calculation. As shown in FIG. 7, the smaller the angle (.theta.) is, the greater the ratio (E.sub.EDGE /E.sub.FLAT) is.
FIGS. 8A through 8C schematically show cross sectional features of the storage node 10 in memory cells having different sizes. As shown in FIGS. 8A through 8C, as the size of the memory cell becomes smaller, the angle of the edges become smaller (.theta..sub.1 &gt;.theta..sub.2 &gt;.theta..sub.3).
In order to reduce the device dimensions without reducing the capacitance of the storage capacitor, it is required to use a stacked capacitor structure having a thinner dielectric film. However, in the prior art devices, an increase in the number of sharp edges of the storage node and a decrease in the thickness of the dielectric film cause the dielectric film to easily break down at a lower voltage.